From 07ddaabc49362f672e0d4f52f57220aac7af39cf Mon Sep 17 00:00:00 2001
From: Thomas White <taw@physics.org>
Date: Thu, 21 Jun 2018 20:03:16 +0200
Subject: Split into separate files and tidy up

---
 src/main.s | 73 ++++++++++++++++++++++++++++----------------------------------
 1 file changed, 33 insertions(+), 40 deletions(-)

(limited to 'src/main.s')

diff --git a/src/main.s b/src/main.s
index a9f7af3..b981b2a 100644
--- a/src/main.s
+++ b/src/main.s
@@ -1,6 +1,27 @@
-@ Tiny bare metal example
+/*
+ * main.s
+ *
+ * Copyright © 2018 Thomas White <taw@bitwiz.org.uk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
 @ vim:ft=armv5
 
+.include "swi_numbers.h"
+
 .section .init
 
 _start:
@@ -25,7 +46,7 @@ hang:
 	B	hang
 
 reset:
-	@ Get out of HYP mode
+	/* Get out of HYP mode */
 	MRS	R0, CPSR
 	BIC	R0, R0, #0x1f
 	ORR	R0, R0, #0x13
@@ -34,9 +55,10 @@ reset:
 	MSR	ELR_hyp,r0
 	ERET
 
-	LDR	R13, =stack_svc		@ Set up stack for SVC mode
+	/* Set up supervisor mode stack */
+	LDR	R13, =stack_svc
 
-	@ Relocate vector table
+	/* Relocate vector table */
 	MOV	R10, #0x8000
 	MOV	R11, #0
 	LDMIA	R10!, {R0-R7}
@@ -44,9 +66,10 @@ reset:
 	LDMIA	R10!, {R0-R7}
 	STMIA	R11!, {R0-R7}
 
-	LDR R0, =start_cpu1
+	/* Set another CPU doing something */
+	LDR R0, =flash_status_led
 	MOV R1, #0x40000000
-	STR R0,[R1, #0xac]
+	STR R0,[R1, #0xbc]
 	SEV
 
 	LDR	R8, =0x3f200000
@@ -87,32 +110,6 @@ repeat:
 	B	repeat
 
 
-start_cpu1:
-	LDR	R8, =0x3f200000
-	LDR	R1, [R8, #0x04]		@ GPFSEL1
-	ORR	R1, R1, #1<<18		@ GPIO pin 16 is output
-	BIC	R1, R1, #3<<21		@ GPIO pin 17 is input
-	ORR	R1, R1, #1<<24		@ GPIO pin 18 is output
-	STR	R1, [R8, #0x04]		@ GPFSEL1
-
-forever:
-	MRC	P15, 0, R0, C0, C0, 5
-	AND	R0, R0, #0x0f
-flashred:
-	MOV	R1, #1<<29
-	STR	R1, [R8, #0x1c]		@ GPSET0
-	BL	longpause
-	MOV	R1, #1<<29
-	STR	R1, [R8, #0x28]		@ GPCLR0
-	BL	longpause
-	SUBS	R0, R0, #1
-	BNE	flashred
-
-	BL	longpause
-	BL	longpause
-	BL	longpause
-	B	forever
-
 swi_handler:
 	STMDB	R13!, {R8, LR}
 	LDR	R8, =0x3f200000
@@ -131,7 +128,7 @@ flash:
 	STMDB	R13!, {R1, R2, R4, LR}
 	MOV	R4, #5
 
-flashloop:
+1:
 	MOV	R1, #1<<16
 	STR	R1, [R8, #0x28]		@ GPCLR0
 	MOV	R1, #1<<18
@@ -151,17 +148,13 @@ flashloop:
 	STR	R1, [R8, #0x28]		@ GPCLR0
 
 	SUBS	R4, R4, #1
-	BNE	flashloop
+	BNE	1b
 
 	LDMIA	R13!, {R1, R2, R4, PC}
 
 pause:
 	MOV	R2, #0x3f000
-wait:
+1:
 	SUBS	R2, R2, #1
-	BNE	wait
+	BNE	1b
 	MOV	PC, LR
-
-longpause:
-	MOV	R2, #0x3f0000
-	B	wait
-- 
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