From 07ddaabc49362f672e0d4f52f57220aac7af39cf Mon Sep 17 00:00:00 2001 From: Thomas White Date: Thu, 21 Jun 2018 20:03:16 +0200 Subject: Split into separate files and tidy up --- src/slow_status_flash.s | 57 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 src/slow_status_flash.s (limited to 'src/slow_status_flash.s') diff --git a/src/slow_status_flash.s b/src/slow_status_flash.s new file mode 100644 index 0000000..afb7be4 --- /dev/null +++ b/src/slow_status_flash.s @@ -0,0 +1,57 @@ +/* + * slow_status_flash.s + * + * Copyright © 2018 Thomas White + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +@ vim:ft=armv5 + +.section .text +.global flash_status_led + +flash_status_led: + LDR R8, =0x3f200000 + LDR R1, [R8, #0x04] @ GPFSEL1 + ORR R1, R1, #1<<18 @ GPIO pin 16 is output + BIC R1, R1, #3<<21 @ GPIO pin 17 is input + ORR R1, R1, #1<<24 @ GPIO pin 18 is output + STR R1, [R8, #0x04] @ GPFSEL1 + +forever: + MRC P15, 0, R0, C0, C0, 5 + AND R0, R0, #0x0f +flashred: + MOV R1, #1<<29 + STR R1, [R8, #0x1c] @ GPSET0 + BL longpause + MOV R1, #1<<29 + STR R1, [R8, #0x28] @ GPCLR0 + BL longpause + SUBS R0, R0, #1 + BNE flashred + + BL longpause + BL longpause + BL longpause + B forever + +longpause: + MOV R2, #0x3f0000 +1: + SUBS R2, R2, #1 + BNE 1b + MOV PC, LR -- cgit v1.2.3