diff options
| author | Graf Yang <graf.yang@analog.com> | 2009-05-08 07:42:12 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-12 06:11:31 -0400 |
| commit | e522c8466d6f8437cf02a34287c8707ef53081ed (patch) | |
| tree | d5f378f4b3a7fb0b0acc5ead4e01b84a6b546b93 | |
| parent | a9a59e3096443ea4d6f50db978d7d3bbb47708b4 (diff) | |
Blackfin: work around anomaly 05000287
Make sure we work around anomaly 05000287 by configuring different port
preferences for the data cache.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| -rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cacheinit.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c index c6ff947f9d3..d5a86c3017f 100644 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) } ctrl = bfin_read_DMEM_CONTROL(); - ctrl |= DMEM_CNTR; + + /* + * Anomaly notes: + * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL + * register, so that the port preferences for DAG0 and DAG1 are set + * to port B + */ + ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); bfin_write_DMEM_CONTROL(ctrl); SSYNC(); } |