diff options
| author | Andrew Vasquez <andrew.vasquez@qlogic.com> | 2007-09-20 14:07:38 -0700 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.localdomain> | 2007-10-12 14:49:54 -0400 |
| commit | c3b058afaea11273835f59694f8645a89915be9c (patch) | |
| tree | b89494dd44d9aa4b088848aff9034c89cb4056ed | |
| parent | 05236a050f8e3a20962bad98ad8ceb94bbdb748c (diff) | |
[SCSI] qla2xxx: Correct staging of RISC while attempting to pause.
There's no need to reset the RISC prior to pausing.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index b52fa8977d9..2defe0c21df 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -172,19 +172,16 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) int rval = QLA_SUCCESS; uint32_t cnt; - if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) { - WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET | - HCCRX_CLR_HOST_INT); - RD_REG_DWORD(®->hccr); /* PCI Posting. */ - WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); - for (cnt = 30000; - (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && - rval == QLA_SUCCESS; cnt--) { - if (cnt) - udelay(100); - else - rval = QLA_FUNCTION_TIMEOUT; - } + if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) + return rval; + + WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); + for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && + rval == QLA_SUCCESS; cnt--) { + if (cnt) + udelay(100); + else + rval = QLA_FUNCTION_TIMEOUT; } return rval; |