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authorThara Gopinath <thara@ti.com>2009-12-08 16:33:15 -0700
committerpaul <paul@twilight.(none)>2009-12-11 17:00:42 -0700
commit3863c74b512c1afd3ce6b2f81d8dea9f1d860968 (patch)
tree1d7d15664c0ae3a71be7949e9c52ca2f79a73811
parent18862cbe47e37beba98f22c088fbe6fe029df889 (diff)
OMAP3: PM: Fix for MPU power domain MEM BANK position
MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap2/powerdomain.c6
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h1
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h5
3 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 47d576883d5..26b3f3ee82a 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -983,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
if (pwrdm->banks < (bank + 1))
return -EEXIST;
+ if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+ bank = 1;
+
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
@@ -1030,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
if (pwrdm->banks < (bank + 1))
return -EEXIST;
+ if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+ bank = 1;
+
/*
* The register bit names below may not correspond to the
* actual names of the bits in each powerdomain's register,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index fd09b0827df..588f7e07d0e 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
.wkdep_srcs = mpu_34xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .flags = PWRDM_HAS_MPU_QUIRK,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 56bb1b9bf2b..0b960051eae 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -42,7 +42,10 @@
/* Powerdomain flags */
#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
-
+#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+ * in MEM bank 1 position. This is
+ * true for OMAP3430
+ */
/*
* Number of memory banks that are power-controllable. On OMAP3430, the