diff options
| author | Mike McCormack <mikem@ring3k.org> | 2009-08-14 05:15:13 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-08-14 15:29:57 -0700 |
| commit | a510996bea68eec2feb7818e9a440bd840613a25 (patch) | |
| tree | a9222e4fbc58b0f20a8c7ec1c14bee1b430e3853 | |
| parent | 9b289c3374d2891aac6c12de58e49a16cfbcb6b1 (diff) | |
sky2: Move tx reset functionality to sky2_tx_reset()
This is pure refactoring.
Signed-off-by: Mike McCormack <mikem@ring3k.org>
Acked-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/sky2.c | 44 |
1 files changed, 26 insertions, 18 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index a52b8631783..768ed47da9b 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c @@ -1811,6 +1811,31 @@ static void sky2_tx_clean(struct net_device *dev) netif_tx_unlock_bh(dev); } +static void sky2_tx_reset(struct sky2_port* sky2) +{ + unsigned port = sky2->port; + struct sky2_hw *hw = sky2->hw; + + /* Disable Force Sync bit and Enable Alloc bit */ + sky2_write8(hw, SK_REG(port, TXA_CTRL), + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); + + /* Stop Interval Timer and Limit Counter of Tx Arbiter */ + sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); + sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); + + /* Reset the PCI FIFO of the async Tx queue */ + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), + BMU_RST_SET | BMU_FIFO_RST); + + /* Reset the Tx prefetch units */ + sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), + PREF_UNIT_RST_SET); + + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); +} + /* Network shutdown */ static int sky2_down(struct net_device *dev) { @@ -1852,26 +1877,9 @@ static int sky2_down(struct net_device *dev) && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); - /* Disable Force Sync bit and Enable Alloc bit */ - sky2_write8(hw, SK_REG(port, TXA_CTRL), - TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); - - /* Stop Interval Timer and Limit Counter of Tx Arbiter */ - sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); - sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); - - /* Reset the PCI FIFO of the async Tx queue */ - sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), - BMU_RST_SET | BMU_FIFO_RST); - - /* Reset the Tx prefetch units */ - sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), - PREF_UNIT_RST_SET); - - sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); + sky2_tx_reset(sky2); sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); - sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); /* Force any delayed status interrrupt and NAPI */ sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); |