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authorMike Mason <mmlnx@us.ibm.com>2008-07-09 02:04:35 +1000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-07-09 16:30:48 +1000
commitcde274c0c789404df8ece3f9e7d6506caf0127e2 (patch)
treec0972e3907077f379289349ac09277ebc58ebb2d
parentb887ec620a7575f54fa025d38fa1008dc8a3b12a (diff)
powerpc/eeh: PERR/SERR bit settings during EEH device recovery
The following patch restores the PERR and SERR bits in the PCI command register during an EEH device recovery. We have found at least one case (an Agilent test card) where the PERR/SERR bits are set to 1 by firmware at boot time, but are not restored to 1 during EEH recovery. The patch fixes the Agilent card problem. It has been tested on several other EEH-enabled cards with no regressions. Signed-off-by: Mike Mason <mmlnx@us.ibm.com> Acked-by: Linas Vepstas <linasvepstas@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-rw-r--r--arch/powerpc/platforms/pseries/eeh.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 6f544ba4b37..c027f0a70a0 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -812,6 +812,7 @@ int rtas_set_slot_reset(struct pci_dn *pdn)
static inline void __restore_bars (struct pci_dn *pdn)
{
int i;
+ u32 cmd;
if (NULL==pdn->phb) return;
for (i=4; i<10; i++) {
@@ -832,6 +833,19 @@ static inline void __restore_bars (struct pci_dn *pdn)
/* max latency, min grant, interrupt pin and line */
rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+
+ /* Restore PERR & SERR bits, some devices require it,
+ don't touch the other command bits */
+ rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+ if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+ cmd |= PCI_COMMAND_PARITY;
+ else
+ cmd &= ~PCI_COMMAND_PARITY;
+ if (pdn->config_space[1] & PCI_COMMAND_SERR)
+ cmd |= PCI_COMMAND_SERR;
+ else
+ cmd &= ~PCI_COMMAND_SERR;
+ rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
}
/**