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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2005-11-24 11:39:29 +0900
committerGreg Kroah-Hartman <gregkh@suse.de>2006-01-09 12:13:17 -0800
commitf467f6187fc60c954a9509b3a3e17ef89a4f6f22 (patch)
tree0ca31955b2de33ec04d22336d0648c2150160e7e
parent0455986cce45d28511f59a29d6cecc17d6b65720 (diff)
[PATCH] shpchp: fix improper write to Command Completion Detect bit
Current SHPCHP driver writes a '0' to the Command Completion Detect bit to clear the Command Complete Interrupt Pending. But according to the SHPC spec (See 4.7.3.1 System Interrupts), SHPCHP driver must write '1'. This patch fixes this bug. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index d82987f075b..f25e1164507 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -1058,11 +1058,11 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
if (intr_loc & 0x0001) {
/*
* Command Complete Interrupt Pending
- * RO only - clear by writing 0 to the Command Completion
+ * RO only - clear by writing 1 to the Command Completion
* Detect bit in Controller SERR-INT register
*/
temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
- temp_dword &= 0xfffeffff;
+ temp_dword &= 0xfffdffff;
writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
wake_up_interruptible(&ctrl->queue);
}