diff options
| author | Michael Chan <mchan@broadcom.com> | 2006-12-17 17:08:07 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-12-17 21:59:22 -0800 |
| commit | 60189ddff03ffce1f0442a7591b2abafdf47e6a3 (patch) | |
| tree | 25d3c5c8211fd57942ae0a57d82c66ad4b2110c5 | |
| parent | c49a1561ee4b663d2819b5bea3e4684eae217b19 (diff) | |
[TG3]: Power down/up 5906 PHY correctly.
The 5906 PHY requires a special register bit to power down and up the
PHY.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/tg3.c | 17 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 1 |
2 files changed, 17 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 501ea6da03c..27c73b9ec2d 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -959,6 +959,13 @@ static int tg3_phy_reset(struct tg3 *tp) u32 phy_status; int err; + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { + u32 val; + + val = tr32(GRC_MISC_CFG); + tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); + udelay(40); + } err = tg3_readphy(tp, MII_BMSR, &phy_status); err |= tg3_readphy(tp, MII_BMSR, &phy_status); if (err != 0) @@ -1170,7 +1177,15 @@ static void tg3_power_down_phy(struct tg3 *tp) if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) return; - if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { + u32 val; + + tg3_bmcr_reset(tp); + val = tr32(GRC_MISC_CFG); + tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); + udelay(40); + return; + } else { tg3_writephy(tp, MII_TG3_EXT_CTRL, MII_TG3_EXT_CTRL_FORCE_LED_OFF); tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index dfaf4ed127b..cf78a7e5997 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1350,6 +1350,7 @@ #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 +#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 #define GRC_LOCAL_CTRL 0x00006808 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 |