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authorNaveen Gupta <ngupta@google.com>2005-08-17 09:11:46 +0200
committerWim Van Sebroeck <wim@iguana.be>2005-09-11 21:51:18 +0200
commitce2f50b4ae71f700c7b4b0bf0ff11c328611dae8 (patch)
tree52570a06396baa2fa96eafe4b7403b9328b676ed
parent28562af3d4b21d687dd57c44006aeeed1036c781 (diff)
[WATCHDOG] i6300esb-set_correct_reload_register_bit
This patch writes into bit 8 of the reload register to perform the correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for Intel 6300ESB chipset. Signed-off-by: Naveen Gupta <ngupta@google.com> Signed-off-by: David Hardeman <david@2gen.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Signed-off-by: Andrew Morton <akpm@osdl.org>
-rw-r--r--drivers/char/watchdog/i6300esb.c6
-rw-r--r--drivers/char/watchdog/i6300esb.h2
2 files changed, 5 insertions, 3 deletions
diff --git a/drivers/char/watchdog/i6300esb.c b/drivers/char/watchdog/i6300esb.c
index f0e96fbd648..c04b246858a 100644
--- a/drivers/char/watchdog/i6300esb.c
+++ b/drivers/char/watchdog/i6300esb.c
@@ -109,7 +109,7 @@ static int esb_timer_stop(void)
spin_lock(&esb_lock);
/* First, reset timers as suggested by the docs */
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* Then disable the WDT */
pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
@@ -123,7 +123,7 @@ static void esb_timer_keepalive(void)
{
spin_lock(&esb_lock);
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush anything here? */
spin_unlock(&esb_lock);
}
@@ -153,7 +153,7 @@ static int esb_timer_set_heartbeat(int time)
/* Reload */
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush everything out? */
diff --git a/drivers/char/watchdog/i6300esb.h b/drivers/char/watchdog/i6300esb.h
index b5b47e3dda1..20c923bbb1c 100644
--- a/drivers/char/watchdog/i6300esb.h
+++ b/drivers/char/watchdog/i6300esb.h
@@ -54,6 +54,8 @@
#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
+/* Reload register bits */
+#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */
/*
* Some magic constants