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authorArnaud Giersch <arnaud.giersch@free.fr>2005-11-13 00:38:18 +0100
committerRalf Baechle <ralf@linux-mips.org>2005-11-17 16:23:47 +0000
commit84c493d8e143360cfba3efede97e5a93d62c4d3d (patch)
tree1530db463632b6cdb279aa0078d2249452d815aa
parent19ce1cfb2d53e5b9f70d0199d551789db2718e6f (diff)
[MIPS] IP32 Fix and complete IP32 parport definitions
Fix, complete, and indent IP32 parport definitions. Definition were wrong for CTXINUSE and DMACTIVE (1-bit shift). Add macros DATA_BOUND, DATALEN_SHIFT, and CTRSHIFT. Signed-off-by: Arnaud Giersch <arnaud.giersch@free.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--include/asm-mips/ip32/mace.h42
1 files changed, 26 insertions, 16 deletions
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 5bdc51d85b6..e514efe44c0 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -150,24 +150,34 @@ struct mace_audio {
/* register definitions for parallel port DMA */
struct mace_parport {
-/* 0 - do nothing, 1 - pulse terminal count to the device after buffer is drained */
-#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
-/* Should not cross 4K page boundary */
-#define MACEPAR_CONTEXT_DATALEN_MASK 0xfff00000000
-/* Can be arbitrarily aligned on any byte boundary on output, 64 byte aligned on input */
-#define MACEPAR_CONTEXT_BASEADDR_MASK 0xffffffff
+ /* 0 - do nothing,
+ * 1 - pulse terminal count to the device after buffer is drained */
+#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
+ /* Should not cross 4K page boundary */
+#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL
+#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL
+#define MACEPAR_CONTEXT_DATALEN_SHIFT 32
+ /* Can be arbitrarily aligned on any byte boundary on output,
+ * 64 byte aligned on input */
+#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL
volatile u64 context_a;
volatile u64 context_b;
-#define MACEPAR_CTLSTAT_DIRECTION BIT(0) /* 0 - mem->device, 1 - device->mem */
-#define MACEPAR_CTLSTAT_ENABLE BIT(1) /* 0 - channel frozen, 1 - channel enabled */
-#define MACEPAR_CTLSTAT_RESET BIT(2) /* 0 - channel active, 1 - complete channel reset */
-#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
-#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
- volatile u64 cntlstat; /* Control/Status register */
-#define MACEPAR_DIAG_CTXINUSE BIT(1)
-#define MACEPAR_DIAG_DMACTIVE BIT(2) /* 1 - Dma engine is enabled and processing something */
-#define MACEPAR_DIAG_CTRMASK 0x3ffc /* Counter of bytes left */
- volatile u64 diagnostic; /* RO: diagnostic register */
+ /* 0 - mem->device, 1 - device->mem */
+#define MACEPAR_CTLSTAT_DIRECTION BIT(0)
+ /* 0 - channel frozen, 1 - channel enabled */
+#define MACEPAR_CTLSTAT_ENABLE BIT(1)
+ /* 0 - channel active, 1 - complete channel reset */
+#define MACEPAR_CTLSTAT_RESET BIT(2)
+#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
+#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
+ volatile u64 cntlstat; /* Control/Status register */
+#define MACEPAR_DIAG_CTXINUSE BIT(0)
+ /* 1 - Dma engine is enabled and processing something */
+#define MACEPAR_DIAG_DMACTIVE BIT(1)
+ /* Counter of bytes left */
+#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL
+#define MACEPAR_DIAG_CTRSHIFT 2
+ volatile u64 diagnostic; /* RO: diagnostic register */
};
/* ISA Control and DMA registers */