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authorStephane Eranian <eranian@hpl.hp.com>2006-12-07 02:14:00 +0100
committerAndi Kleen <andi@basil.nowhere.org>2006-12-07 02:14:00 +0100
commitbd1d599518bf11992cc6d5b0df08da4a2b7b0db5 (patch)
tree214b6a571c6a77b5b58e9019c3e166ff10e76032
parent87e1652c7863b9ae406ff37f33c7ec2bb494d7b1 (diff)
[PATCH] x86-64: x86_64 rename X86_FEATURE_DTES to X86_FEATURE_DS
Here is a patch (used by perfmon2) that renamed X86_FEATURE_DTES to X86_FEATURE_DS to match Intel's documentation for the Debug Store save area. The patch also adds cpu_has_ds. changelog: - rename X86_FEATURE_DTES to X86_FEATURE_DS to match documentation - adds cpu_has_ds to test for X86_FEATURE_DS Signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de>
-rw-r--r--include/asm-x86_64/cpufeature.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h
index ee792faaca0..65eb39e8f3c 100644
--- a/include/asm-x86_64/cpufeature.h
+++ b/include/asm-x86_64/cpufeature.h
@@ -29,7 +29,7 @@
#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
-#define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */
+#define X86_FEATURE_DS (0*32+21) /* Debug Store */
#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
@@ -112,5 +112,6 @@
#define cpu_has_cyrix_arr 0
#define cpu_has_centaur_mcr 0
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
+#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
#endif /* __ASM_X8664_CPUFEATURE_H */