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authorPJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>2009-04-16 15:00:20 +0000
committerDavid S. Miller <davem@davemloft.net>2009-04-17 01:16:28 -0700
commitf92ef202988ffb07bb86cf94d0b09f2a61192da7 (patch)
tree7cbce5e0e9dde2b619c8c92855242a6408178539
parent843f42678f6c47a2c8d1648e584cb57ebff3750f (diff)
ixgbe: Fix DCB traffic class mapping for 82599
The traffic classes in hardware are not symmetrical for Rx and Tx. Rx is every 16 descriptor queues, Tx is not. It runs 32-32-16-16-8-8-8 when running with 8 traffic classes, and runs 64-32-16 when running with 4 traffic classes. This patch fixes the mapping. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Cc: stable@kernel.org Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c52
1 files changed, 48 insertions, 4 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 49a90378456..01884256f4c 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -2841,11 +2841,55 @@ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
}
ret = true;
} else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
- for (i = 0; i < dcb_i; i++) {
- adapter->rx_ring[i].reg_idx = i << 4;
- adapter->tx_ring[i].reg_idx = i << 4;
+ if (dcb_i == 8) {
+ /*
+ * Tx TC0 starts at: descriptor queue 0
+ * Tx TC1 starts at: descriptor queue 32
+ * Tx TC2 starts at: descriptor queue 64
+ * Tx TC3 starts at: descriptor queue 80
+ * Tx TC4 starts at: descriptor queue 96
+ * Tx TC5 starts at: descriptor queue 104
+ * Tx TC6 starts at: descriptor queue 112
+ * Tx TC7 starts at: descriptor queue 120
+ *
+ * Rx TC0-TC7 are offset by 16 queues each
+ */
+ for (i = 0; i < 3; i++) {
+ adapter->tx_ring[i].reg_idx = i << 5;
+ adapter->rx_ring[i].reg_idx = i << 4;
+ }
+ for ( ; i < 5; i++) {
+ adapter->tx_ring[i].reg_idx =
+ ((i + 2) << 4);
+ adapter->rx_ring[i].reg_idx = i << 4;
+ }
+ for ( ; i < dcb_i; i++) {
+ adapter->tx_ring[i].reg_idx =
+ ((i + 8) << 3);
+ adapter->rx_ring[i].reg_idx = i << 4;
+ }
+
+ ret = true;
+ } else if (dcb_i == 4) {
+ /*
+ * Tx TC0 starts at: descriptor queue 0
+ * Tx TC1 starts at: descriptor queue 64
+ * Tx TC2 starts at: descriptor queue 96
+ * Tx TC3 starts at: descriptor queue 112
+ *
+ * Rx TC0-TC3 are offset by 32 queues each
+ */
+ adapter->tx_ring[0].reg_idx = 0;
+ adapter->tx_ring[1].reg_idx = 64;
+ adapter->tx_ring[2].reg_idx = 96;
+ adapter->tx_ring[3].reg_idx = 112;
+ for (i = 0 ; i < dcb_i; i++)
+ adapter->rx_ring[i].reg_idx = i << 5;
+
+ ret = true;
+ } else {
+ ret = false;
}
- ret = true;
} else {
ret = false;
}