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authorMichael Hennerich <michael.hennerich@analog.com>2008-04-24 07:32:41 +0800
committerBryan Wu <cooloney@kernel.org>2008-04-24 07:32:41 +0800
commita81501af19830ff43688781edad7e9c0cbd668af (patch)
tree856be99eb74bfc5e6cf20369b633107d8d4170f6 /CREDITS
parent4bea8b20fded93871c872bb4a0d7c23345318184 (diff)
[Blackfin] arch: Prevent potential Core Hang situation
If the new value written to the PLL_CTL or VR_CTL register is the same as the previous value, the PLL wake-up will occur immediately (PLL is already locked), but the core and system clock will be bypassed for the PLL_LOCKCNT duration. For this interval, code will execute at the CLKIN rate instead of at the expected CCLK rate. Software should guard against this condition by comparing the current value to the new value before writing the new value. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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