aboutsummaryrefslogtreecommitdiff
path: root/Documentation/arm/Sharp-LH/IOBarrier
diff options
context:
space:
mode:
authorUwe Kleine-König <Uwe.Kleine-Koenig@digi.com>2008-02-03 14:59:11 +0200
committerAdrian Bunk <bunk@kernel.org>2008-02-03 14:59:11 +0200
commita247b5d594aafe3a0121ae658a974cbea32e18d6 (patch)
tree36cbdb622ee4d6e36a2ef5a00cbc64fba71465f7 /Documentation/arm/Sharp-LH/IOBarrier
parentb885b27ce67013a7aa7f4181fdd916a29c623850 (diff)
fix typo 'the same the\>'
Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'Documentation/arm/Sharp-LH/IOBarrier')
-rw-r--r--Documentation/arm/Sharp-LH/IOBarrier2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arm/Sharp-LH/IOBarrier b/Documentation/arm/Sharp-LH/IOBarrier
index c0d8853672d..2e953e228f4 100644
--- a/Documentation/arm/Sharp-LH/IOBarrier
+++ b/Documentation/arm/Sharp-LH/IOBarrier
@@ -32,7 +32,7 @@ BARRIER IO before the access to the SMC chip because the AEN latch
only needs occurs after the SMC IO write cycle. The routines that
implement this work-around make an additional concession which is to
disable interrupts during the IO sequence. Other hardware devices
-(the LogicPD CPLD) have registers in the same the physical memory
+(the LogicPD CPLD) have registers in the same physical memory
region as the SMC chip. An interrupt might allow an access to one of
those registers while SMC IO is being performed.