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author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-04-29 14:14:35 -0400 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2009-05-19 00:50:23 -0500 |
commit | 345f84227b50e90329dd303499024603596566f4 (patch) | |
tree | 609868e873f374aacdbb58a37db8de4517bf4d8e /Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt | |
parent | 06c4435021f4856261edd01e2691071edeb8fa51 (diff) |
net/ucc_geth: update riscTx and riscRx in ucc_geth
Change the definition of riscTx and riscRx to unsigned integer instead of
enum, and change their values to support 4 risc allocation if the qe has
4 RISC engines.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt')
0 files changed, 0 insertions, 0 deletions