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authorMaciej W. Rozycki <macro@linux-mips.org>2006-10-02 12:55:09 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-10-03 17:59:17 +0100
commit15a1c5140436c5be7673a4709c5d7e1f3cd7bdd9 (patch)
tree0ec2b255917f916c072af27eeeb2b76d9d361ff9 /Documentation
parent3a42aa934856bfe3f28946f66ea8a5f056445747 (diff)
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems
It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
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