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authorIngo Molnar <mingo@elte.hu>2008-08-26 10:25:59 +0200
committerIngo Molnar <mingo@elte.hu>2008-08-26 10:25:59 +0200
commit3cf430b0636045dc524759a0852293ba037732a7 (patch)
tree2c4e03f9028dc23ab4e6ca5a3a5a263af397984f /arch/alpha/include/asm/cache.h
parent93dcf55f828b035fc93fc19eb03c1390e1e6d570 (diff)
parent83097aca8567a0bd593534853b71fe0fa9a75d69 (diff)
Merge branch 'linus' into sched/devel
Diffstat (limited to 'arch/alpha/include/asm/cache.h')
-rw-r--r--arch/alpha/include/asm/cache.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/alpha/include/asm/cache.h b/arch/alpha/include/asm/cache.h
new file mode 100644
index 00000000000..f199e69a5d0
--- /dev/null
+++ b/arch/alpha/include/asm/cache.h
@@ -0,0 +1,23 @@
+/*
+ * include/asm-alpha/cache.h
+ */
+#ifndef __ARCH_ALPHA_CACHE_H
+#define __ARCH_ALPHA_CACHE_H
+
+
+/* Bytes per L1 (data) cache line. */
+#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
+# define L1_CACHE_BYTES 64
+# define L1_CACHE_SHIFT 6
+#else
+/* Both EV4 and EV5 are write-through, read-allocate,
+ direct-mapped, physical.
+*/
+# define L1_CACHE_BYTES 32
+# define L1_CACHE_SHIFT 5
+#endif
+
+#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+
+#endif