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author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2009-06-11 01:58:01 -0700 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2009-06-11 01:58:01 -0700 |
commit | 4894e4aca82aca927d0404ce61f021f790de4b1e (patch) | |
tree | bbe0d083829f5858295298f188d885367cf4b1f6 /arch/arm/include/asm/cache.h | |
parent | 05e882f890038c702a4f15d385135d03cf74ad48 (diff) | |
parent | 07a2039b8eb0af4ff464efd3dfd95de5c02648c6 (diff) |
Merge commit 'v2.6.30' into next
Diffstat (limited to 'arch/arm/include/asm/cache.h')
-rw-r--r-- | arch/arm/include/asm/cache.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index cb7a9e97fd7..feaa75f0013 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -7,4 +7,20 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + +/* + * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. + */ +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) +#define ARCH_SLAB_MINALIGN 8 +#endif + #endif |