diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-14 17:48:14 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-14 17:48:14 -0700 |
commit | 2ca7d674d7ab2220707b2ada0b690c0e7c95e7ac (patch) | |
tree | 9c0927ed1d540e5fd704c1f82689870786514655 /arch/arm/mach-bcmring/clock.c | |
parent | 2195d2818c37bdf263865f1e9effccdd9fc5f9d4 (diff) | |
parent | 87d721ad7a37b7650dd710c88dd5c6a5bf9fe996 (diff) |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (257 commits)
[ARM] Update mach-types
ARM: 5636/1: Move vendor enum to AMBA include
ARM: Fix pfn_valid() for sparse memory
[ARM] orion5x: Add LaCie NAS 2Big Network support
[ARM] pxa/sharpsl_pm: zaurus c3000 aka spitz: fix resume
ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek board
ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek board
ARM: 5689/1: Update default config of HP Jornada 700-series machines
ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
ARM: 5688/1: ks8695_serial: disable_irq() lockup
ARM: 5687/1: fix an oops with highmem
ARM: 5684/1: Add nuc960 platform to w90x900
ARM: 5683/1: Add nuc950 platform to w90x900
ARM: 5682/1: Add cpu.c and dev.c and modify some files of w90p910 platform
ARM: 5626/1: add suspend/resume functions to amba-pl011 serial driver
ARM: 5625/1: fix hard coded 4K resource size in amba bus detection
MMC: MMCI: convert realview MMC to use gpiolib
ARM: 5685/1: Make MMCI driver compile without gpiolib
ARM: implement highpte
ARM: Show FIQ in /proc/interrupts on CONFIG_FIQ
...
Fix up trivial conflict in arch/arm/kernel/signal.c.
It was due to the TIF_NOTIFY_RESUME addition in commit d0420c83f ("KEYS:
Extend TIF_NOTIFY_RESUME to (almost) all architectures") and follow-ups.
Diffstat (limited to 'arch/arm/mach-bcmring/clock.c')
-rw-r--r-- | arch/arm/mach-bcmring/clock.c | 224 |
1 files changed, 224 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c new file mode 100644 index 00000000000..14bafc38f2d --- /dev/null +++ b/arch/arm/mach-bcmring/clock.c @@ -0,0 +1,224 @@ +/***************************************************************************** +* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include <mach/csp/hw_cfg.h> +#include <mach/csp/chipcHw_def.h> +#include <mach/csp/chipcHw_reg.h> +#include <mach/csp/chipcHw_inline.h> + +#include <asm/clkdev.h> + +#include "clock.h" + +#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) +#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1) +#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2) +#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) +#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE) + +#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL) + +static DEFINE_SPINLOCK(clk_lock); + +static void __clk_enable(struct clk *clk) +{ + if (!clk) + return; + + /* enable parent clock first */ + if (clk->parent) + __clk_enable(clk->parent); + + if (clk->use_cnt++ == 0) { + if (clk_is_pll1(clk)) { /* PLL1 */ + chipcHw_pll1Enable(clk->rate_hz, 0); + } else if (clk_is_pll2(clk)) { /* PLL2 */ + chipcHw_pll2Enable(clk->rate_hz); + } else if (clk_is_using_xtal(clk)) { /* source is crystal */ + if (!clk_is_primary(clk)) + chipcHw_bypassClockEnable(clk->csp_id); + } else { /* source is PLL */ + chipcHw_setClockEnable(clk->csp_id); + } + } +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + + if (!clk) + return -EINVAL; + + spin_lock_irqsave(&clk_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clk_lock, flags); + + return 0; +} +EXPORT_SYMBOL(clk_enable); + +static void __clk_disable(struct clk *clk) +{ + if (!clk) + return; + + BUG_ON(clk->use_cnt == 0); + + if (--clk->use_cnt == 0) { + if (clk_is_pll1(clk)) { /* PLL1 */ + chipcHw_pll1Disable(); + } else if (clk_is_pll2(clk)) { /* PLL2 */ + chipcHw_pll2Disable(); + } else if (clk_is_using_xtal(clk)) { /* source is crystal */ + if (!clk_is_primary(clk)) + chipcHw_bypassClockDisable(clk->csp_id); + } else { /* source is PLL */ + chipcHw_setClockDisable(clk->csp_id); + } + } + + if (clk->parent) + __clk_disable(clk->parent); +} + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (!clk) + return; + + spin_lock_irqsave(&clk_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clk_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate_hz; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + unsigned long actual; + unsigned long rate_hz; + + if (!clk) + return -EINVAL; + + if (!clk_is_programmable(clk)) + return -EINVAL; + + if (clk->use_cnt) + return -EBUSY; + + spin_lock_irqsave(&clk_lock, flags); + actual = clk->parent->rate_hz; + rate_hz = min(actual, rate); + spin_unlock_irqrestore(&clk_lock, flags); + + return rate_hz; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + unsigned long actual; + unsigned long rate_hz; + + if (!clk) + return -EINVAL; + + if (!clk_is_programmable(clk)) + return -EINVAL; + + if (clk->use_cnt) + return -EBUSY; + + spin_lock_irqsave(&clk_lock, flags); + actual = clk->parent->rate_hz; + rate_hz = min(actual, rate); + rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz); + clk->rate_hz = rate_hz; + spin_unlock_irqrestore(&clk_lock, flags); + + return 0; +} +EXPORT_SYMBOL(clk_set_rate); + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return NULL; + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long flags; + struct clk *old_parent; + + if (!clk || !parent) + return -EINVAL; + + if (!clk_is_primary(parent) || !clk_is_bypassable(clk)) + return -EINVAL; + + /* if more than one user, parent is not allowed */ + if (clk->use_cnt > 1) + return -EBUSY; + + if (clk->parent == parent) + return 0; + + spin_lock_irqsave(&clk_lock, flags); + old_parent = clk->parent; + clk->parent = parent; + if (clk_is_using_xtal(parent)) + clk->mode |= CLK_MODE_XTAL; + else + clk->mode &= (~CLK_MODE_XTAL); + + /* if clock is active */ + if (clk->use_cnt != 0) { + clk->use_cnt--; + /* enable clock with the new parent */ + __clk_enable(clk); + /* disable the old parent */ + __clk_disable(old_parent); + } + spin_unlock_irqrestore(&clk_lock, flags); + + return 0; +} +EXPORT_SYMBOL(clk_set_parent); |