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authorSekhar Nori <nsekhar@ti.com>2009-11-16 17:21:35 +0530
committerKevin Hilman <khilman@deeprootsystems.com>2010-02-04 13:29:36 -0800
commitc94fa15ba2d736af786ac1e56686d41987b1aba0 (patch)
treefa3143cd1ea6029180ee3a69359c05aea9481558 /arch/arm/mach-davinci/include/mach/psc.h
parent7ec4b24326ec9b0467ab23b0417ec6b63e8e5524 (diff)
davinci: move PSC register definitions from psc.c to psc.h
The motivation behind the change is to use the same definitions in the assembly code responsible for suspending the SoC, a part of which is to clock gate the DDR2 clock. Note that the assembly code cannot invoke the C function meant for this. The main reason being that stack in DDR2 cannot be accessed while DDR2 clock is being clock gated. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/include/mach/psc.h')
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 171173c1dba..2776b235659 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,6 +180,17 @@
#define DA8XX_LPSC1_CR_P3_SS 26
#define DA8XX_LPSC1_L3_CBA_RAM 31
+/* PSC register offsets */
+#define EPCPR 0x070
+#define PTCMD 0x120
+#define PTSTAT 0x128
+#define PDSTAT 0x200
+#define PDCTL1 0x304
+#define MDSTAT 0x800
+#define MDCTL 0xA00
+
+#define MDSTAT_STATE_MASK 0x1f
+
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, char enable);