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author | James Morris <jmorris@namei.org> | 2008-08-28 10:47:34 +1000 |
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committer | James Morris <jmorris@namei.org> | 2008-08-28 10:47:34 +1000 |
commit | 86d688984deefa3ae5a802880c11f2b408b5d6cf (patch) | |
tree | 7ea5e8189b0a774626d3ed7c3c87df2495a4c4a0 /arch/arm/mach-iop33x/include/mach/hardware.h | |
parent | 93c06cbbf9fea5d5be1778febb7fa9ab1a74e5f5 (diff) | |
parent | 4c246edd2550304df5b766cc841584b2bb058843 (diff) |
Merge branch 'master' into next
Diffstat (limited to 'arch/arm/mach-iop33x/include/mach/hardware.h')
-rw-r--r-- | arch/arm/mach-iop33x/include/mach/hardware.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h new file mode 100644 index 00000000000..8c10e430655 --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/hardware.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-iop33x/include/mach/hardware.h + */ + +#ifndef __HARDWARE_H +#define __HARDWARE_H + +#include <asm/types.h> + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/mach-iop3xx/iop3xx-pci.c + */ +#define pcibios_assign_all_busses() 1 +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 + +#ifndef __ASSEMBLY__ +void iop33x_init_irq(void); + +extern struct platform_device iop33x_uart0_device; +extern struct platform_device iop33x_uart1_device; +#endif + + +/* + * Generic chipset bits + * + */ +#include "iop33x.h" + +/* + * Board specific bits + */ +#include "iq80331.h" +#include "iq80332.h" + + +#endif |