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authorKrzysztof Hałasa <khc@pm.waw.pl>2009-11-17 18:48:23 +0100
committerKrzysztof Hałasa <khc@pm.waw.pl>2009-12-05 16:58:41 +0100
commit8d3fdf31dd2066533861bb57ed7df1ae1b1f5fcc (patch)
tree5186d63c67dee5454348e55cf46d31053672d67d /arch/arm/mach-ixp4xx/nas100d-pci.c
parenta8b7b34075f693632cd1483b817d4211c7a63257 (diff)
IXP4xx: Introduce IXP4XX_GPIO_IRQ(n) macro and convert IXP4xx platform files.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Diffstat (limited to 'arch/arm/mach-ixp4xx/nas100d-pci.c')
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-pci.c50
1 files changed, 20 insertions, 30 deletions
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index ac04fc1a6c3..d0cea34cf61 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -21,49 +21,39 @@
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
-#define NAS100D_PCI_MAX_DEV 3
-#define NAS100D_PCI_IRQ_LINES 3
+#define MAX_DEV 3
+#define IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
-#define NAS100D_PCI_INTA_PIN 11
-#define NAS100D_PCI_INTB_PIN 10
-#define NAS100D_PCI_INTC_PIN 9
-#define NAS100D_PCI_INTD_PIN 8
-#define NAS100D_PCI_INTE_PIN 7
-
-#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
-#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
-#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
-#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
-#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
+#define INTA 11
+#define INTB 10
+#define INTC 9
+#define INTD 8
+#define INTE 7
void __init nas100d_pci_preinit(void)
{
- set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
- set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
-
+ set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}
static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
- static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] =
- {
- { IRQ_NAS100D_PCI_INTA, -1, -1 },
- { IRQ_NAS100D_PCI_INTB, -1, -1 },
- { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE },
+ static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
+ { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
+ { IXP4XX_GPIO_IRQ(INTB), -1, -1 },
+ { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
+ IXP4XX_GPIO_IRQ(INTE) },
};
- int irq = -1;
-
- if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV &&
- pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES)
- irq = pci_irq_table[slot-1][pin-1];
+ if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+ return pci_irq_table[slot - 1][pin - 1];
- return irq;
+ return -1;
}
struct hw_pci __initdata nas100d_pci = {