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authorPaul Walmsley <paul@pwsan.com>2009-06-19 19:08:26 -0600
committerpaul <paul@twilight.(none)>2009-06-19 19:09:31 -0600
commitc9812d042a21eb492a36cfabf9f41107f5ecee3d (patch)
treef9443de1d4534b0b56bd1b0ff56bfc6d78eb698d /arch/arm/mach-omap2/sram34xx.S
parent2f135eaf182761bb9a5cbd5138a447b0ad2a1fef (diff)
OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/sram34xx.S')
-rw-r--r--arch/arm/mach-omap2/sram34xx.S20
1 files changed, 9 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 84781a6cd26..8d4a88c3071 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -42,10 +42,14 @@
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
* SDRC rates < 83MHz
+ * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ * reprogramming the SDRC when switching to a slower MPU speed
+ *
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack
+ ldr r5, [sp, #56] @ load extra args from the stack
dsb @ flush buffered writes to interconnect
cmp r3, #0x2
blne configure_sdrc
@@ -59,7 +63,11 @@ ENTRY(omap3_sram_configure_core_dpll)
bleq wait_dll_unlock
blne wait_dll_lock
cmp r3, #0x1
- blne configure_sdrc
+ beq return_to_sdram
+ bl configure_sdrc
+ mov r12, r5 @ if slowing, wait for SDRC to stabilize
+ bl wait_clk_stable
+return_to_sdram:
isb @ prevent speculative exec past here
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
@@ -106,16 +114,6 @@ configure_core_dpll:
wait_clk_stable:
subs r12, r12, #1
bne wait_clk_stable
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
bx lr
enable_sdrc:
ldr r11, omap3_cm_iclken1_core