diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-24 08:36:41 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-24 08:36:41 -0700 |
| commit | 6ae85d6db4871d8dbcb5cc0e9056f97f1ca07061 (patch) | |
| tree | d0a6fa2e4fcef36a4c80990a361c0d5fbe091c35 /arch/arm/mach-orion5x/include/mach/bridge-regs.h | |
| parent | d72cd3a90e4d6725b62919139e2ab7bd926fa16d (diff) | |
| parent | fdd8b079e33d4711527ace19798e9db99a056469 (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 5460/1: Orion: reduce namespace pollution
[ARM] 5458/1: pcmcia: pxa2xx-sharpsl: check if we do have Scoop config
[ARM] 5457/1: mach-imx gpio buildfix
[ARM] 5456/1: add sys_preadv and sys_pwritev
[ARM] pxa/pcm990: start external GPIOs immediately after built-in ones
[ARM] pxa/palm27x: General fix for Palm27x aSoC driver
[ARM] pxa/mioa701: use GPIO95 as AC97 reset line
[ARM] pxa: merge AC97 platform data structures
[ARM] pxa/magician: remove un-necessary #include of pxa-regs.h and hardware.h
Diffstat (limited to 'arch/arm/mach-orion5x/include/mach/bridge-regs.h')
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/bridge-regs.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h new file mode 100644 index 00000000000..be896e59d3e --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-orion5x/include/mach/bridge-regs.h + * + * Orion CPU Bridge Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include <mach/orion5x.h> + +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) + +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) + +#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) +#define WDT_RESET 0x0002 + +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) + +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) + +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) +#define WDT_INT_REQ 0x0008 + +#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) + +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) + +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) + +#endif |