aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-s3c2440
diff options
context:
space:
mode:
authorBen Dooks <ben-linux@fluff.org>2008-04-16 00:12:39 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-17 17:04:40 +0100
commitd96a980441a70168a8ead0a0f23c4c63725da5fa (patch)
tree098551e6498fa641caaff62e352d21d7d9383c84 /arch/arm/mach-s3c2440
parent1017be88d341c05adc8d790d8092781b7330dafd (diff)
[ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK
All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2440')
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c5
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 3d3dfa95db8..47258915a2f 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -413,10 +413,10 @@ static void __init anubis_map_io(void)
{
/* initialise the clocks */
- s3c24xx_dclk0.parent = NULL;
+ s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
- s3c24xx_dclk1.parent = NULL;
+ s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 78af7664988..8a8acdbd072 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -18,6 +18,7 @@
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
+#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -344,10 +345,10 @@ static void __init osiris_map_io(void)
/* initialise the clocks */
- s3c24xx_dclk0.parent = NULL;
+ s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
- s3c24xx_dclk1.parent = NULL;
+ s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;