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authorBen Dooks <ben-linux@fluff.org>2008-10-21 14:06:51 +0100
committerBen Dooks <ben-linux@fluff.org>2008-12-15 21:51:22 +0000
commitd9b79fb56829de34eaddb01b405216eddd0d3b10 (patch)
tree3b22ecbb2946d237590f34efd558ac58fb8fc90b /arch/arm/mach-s3c6410
parentd626aeedc96e21a048f1a300cd6360f3a7be10f2 (diff)
[ARM] S3C64XX: Add VIC0 and VIC1 sourced interripts
Add and initialise the two VIC (PL192) found on the S3C64XX series CPUs. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c6410')
-rw-r--r--arch/arm/mach-s3c6410/cpu.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index fbca763fa48..c3e317c1650 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -58,6 +58,12 @@ void __init s3c6410_init_clocks(int xtal)
s3c24xx_register_baseclocks(xtal);
}
+void __init s3c6410_init_irq(void)
+{
+ /* VIC0 is missing IRQ7, VIC1 is fully populated. */
+ s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
+}
+
struct sysdev_class s3c6410_sysclass = {
.name = "s3c6410-core",
};