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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-11-27 12:42:48 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-11-27 12:42:48 +0000 |
| commit | f412b09f4ed7c57f5b8935ed7d6fc786f402a629 (patch) | |
| tree | 34fe1b4b64db4993e9fb21a70812fafed0437870 /arch/arm/mm/cache-v7.S | |
| parent | 31bccbf39208133415000520c79ebe7b291786df (diff) | |
| parent | 7f1fd31db158c95418d9cc5690ab60ecc6fb632d (diff) | |
Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into devel
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index d19c2bec2b1..be93ff02a98 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -26,6 +26,7 @@ * - mm - mm_struct describing address space */ ENTRY(v7_flush_dcache_all) + dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field @@ -64,6 +65,7 @@ skip: finished: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb isb mov pc, lr ENDPROC(v7_flush_dcache_all) |