diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-03 09:05:40 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-03 09:05:40 -0700 |
| commit | 31e6e2dac575c9d21a6ec56ca52ae89086baa705 (patch) | |
| tree | a83dc42a3e4ff2e49e532031ec3e86c402e4baa1 /arch/arm/mm | |
| parent | ea02259fdf47ca81ff3ca0c22906d989094fb8ff (diff) | |
| parent | 67a52bb90b515c2a96ec51a3571bcd70a2fadb50 (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] fix build-breaking 7a192ec commit
ARM: Add SMSC911X support to Overo platform (V2)
arm: update omap_ldp defconfig to use smsc911x
arm: update realview defconfigs to use smsc911x
arm: update pcm037 defconfig to use smsc911x
arm: convert omap ldp platform to use smsc911x
arm: convert realview platform to use smsc911x
arm: convert pcm037 platform to use smsc911x
[ARM] 5444/1: ARM: Realview: Fix event-device multiplicators in localtimer.c
[ARM] 5442/1: pxa/cm-x255: fix reverse RDY gpios in PCMCIA driver
[ARM] 5441/1: Use pr_err on error paths in at91 pm
[ARM] 5440/1: Fix VFP state corruption due to preemption during VFP exceptions
[ARM] 5439/1: Do not clear bit 10 of DFSR during abort handling on ARMv6
[ARM] 5437/1: Add documentation for "nohlt" kernel parameter
[ARM] 5436/1: ARM: OMAP: Fix compile for rx51
[ARM] arch_reset() now takes a second parameter
[ARM] Kirkwood: small L2 code cleanup
[ARM] Kirkwood: invalidate L2 cache before enabling it
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/abort-ev6.S | 4 | ||||
| -rw-r--r-- | arch/arm/mm/cache-feroceon-l2.c | 9 |
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index 94077fbd96b..6f7e70907e4 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -29,10 +29,10 @@ ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR /* - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). * The test below covers all the write situations, including Java bytecodes */ - bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR + bic r1, r1, #1 << 11 @ clear bit 11 of FSR tst r3, #PSR_J_BIT @ Java? movne pc, lr do_thumb_abort diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index d6dd83826f8..6e77c042d8e 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -115,6 +115,10 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end) raw_local_irq_restore(flags); } +static inline void l2_inv_all(void) +{ + __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0)); +} /* * Linux primitives. @@ -254,9 +258,7 @@ static void __init enable_dcache(void) static void __init __invalidate_icache(void) { - int dummy; - - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy)); + __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); } static int __init invalidate_and_disable_icache(void) @@ -321,6 +323,7 @@ static void __init enable_l2(void) d = flush_and_disable_dcache(); i = invalidate_and_disable_icache(); + l2_inv_all(); write_extra_features(u | 0x00400000); if (i) enable_icache(); |