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authorMarek Szyprowski <m.szyprowski@samsung.com>2009-11-19 11:30:30 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-11-24 10:06:26 +0000
commit394168389c5770accf1d255fdfe45846ec121585 (patch)
tree9f5493e46b94a1aed058d121091ea8e982a95d11 /arch/arm/mm
parentb43149c168ce4069ce8828b1ceb8f7eb42bc4b82 (diff)
ARM: 5791/1: ARM: MM: use 64bytes of L1 cache on plat S5PC1xx
Samsung S5PC1xx SoCs are based on ARM Coretex8, which has 64 bytes of L1 cache line size. Enable proper handling of L1 cache on these SoCs. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e993140edd8..9cf7706e0be 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -777,5 +777,5 @@ config CACHE_XSC3L2
config ARM_L1_CACHE_SHIFT
int
- default 6 if ARCH_OMAP3
+ default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
default 5