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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2009-11-10 10:20:30 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2009-11-18 10:40:44 +0100
commite676756fa43e04166111e4729c62bb4fdf477255 (patch)
tree2334b7f48d5b20b9315908b50d4a8b18ac29a6ba /arch/arm/plat-mxc
parentf73a42f7054b4ec7fab373789b7dae1e309f81a7 (diff)
imx: reorder mx3x.h
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h45
1 files changed, 23 insertions, 22 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 009f4440276..3e07d3da104 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -34,21 +34,6 @@
* C0000000 64M PCMCIA/CF
*/
-#define CS0_BASE_ADDR 0xA0000000
-#define CS1_BASE_ADDR 0xA8000000
-#define CS2_BASE_ADDR 0xB0000000
-#define CS3_BASE_ADDR 0xB2000000
-
-#define CS4_BASE_ADDR 0xB4000000
-#define CS4_BASE_ADDR_VIRT 0xF4000000
-#define CS4_SIZE SZ_32M
-
-#define CS5_BASE_ADDR 0xB6000000
-#define CS5_BASE_ADDR_VIRT 0xF6000000
-#define CS5_SIZE SZ_32M
-
-#define PCMCIA_MEM_BASE_ADDR 0xBC000000
-
/*
* L2CC
*/
@@ -101,6 +86,7 @@
#define AIPS2_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR_VIRT 0xFC200000
#define AIPS2_SIZE SZ_1M
+
#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
@@ -130,6 +116,27 @@
#define AVIC_SIZE SZ_1M
/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR 0x70000000
+#define CSD0_BASE_ADDR 0x80000000
+#define CSD1_BASE_ADDR 0x90000000
+
+#define CS0_BASE_ADDR 0xA0000000
+#define CS1_BASE_ADDR 0xA8000000
+#define CS2_BASE_ADDR 0xB0000000
+#define CS3_BASE_ADDR 0xB2000000
+
+#define CS4_BASE_ADDR 0xB4000000
+#define CS4_BASE_ADDR_VIRT 0xF4000000
+#define CS4_SIZE SZ_32M
+
+#define CS5_BASE_ADDR 0xB6000000
+#define CS5_BASE_ADDR_VIRT 0xF6000000
+#define CS5_SIZE SZ_32M
+
+
+/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define X_MEMC_BASE_ADDR 0xB8000000
@@ -142,12 +149,7 @@
#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR 0x70000000
-#define CSD0_BASE_ADDR 0x80000000
-#define CSD1_BASE_ADDR 0x90000000
+#define PCMCIA_MEM_BASE_ADDR 0xBC000000
/*!
* This macro defines the physical to virtual address mapping for all the
@@ -272,4 +274,3 @@ static inline int mx31_revision(void)
#endif
#endif /* __ASM_ARCH_MXC_MX31_H__ */
-