diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-06-19 19:08:27 -0600 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-06-19 19:09:31 -0600 |
| commit | d0ba3922ae241a87d22a1c3ffad72b96fe993c9a (patch) | |
| tree | 3f23d60fbbf2ffceef44b01c8579db7be7d20025 /arch/arm/plat-omap/include/mach | |
| parent | c9812d042a21eb492a36cfabf9f41107f5ecee3d (diff) | |
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/sram.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index c32fa0a220d..4f87056a367 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f); + u32 unlock_dll, u32 f, u32 sdrc_mr); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, - u32 unlock_dll, u32 f); + u32 unlock_dll, u32 f, u32 sdrc_mr); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif |