diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-02-19 13:29:22 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-19 17:28:30 +0000 |
| commit | c0bf31320dea2cbcbab1f53ee15a8520f762409b (patch) | |
| tree | 1b4fbb4396da448eb116f2bee8b58030b63cfe3b /arch/arm/plat-omap/include | |
| parent | 8b9dbc16d4f5786c6c930ab028722e3ed7e4285b (diff) | |
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-omap/include')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/clock.h | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 7b6f6bcbff9..073a2c5569f 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -39,6 +39,10 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; + struct clk *clk_bypass; + struct clk *clk_ref; + void __iomem *control_reg; + u32 enable_mask; unsigned int rate_tolerance; unsigned long last_rounded_rate; u16 last_rounded_m; @@ -49,10 +53,8 @@ struct dpll_data { u16 max_multiplier; # if defined(CONFIG_ARCH_OMAP3) u8 modes; - void __iomem *control_reg; void __iomem *autoidle_reg; void __iomem *idlest_reg; - u32 enable_mask; u32 autoidle_mask; u32 freqsel_mask; u32 idlest_mask; @@ -154,9 +156,4 @@ extern const struct clkops clkops_null; #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) -/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ -#define CORE_CLK_SRC_32K 0 -#define CORE_CLK_SRC_DPLL 1 -#define CORE_CLK_SRC_DPLL_X2 2 - #endif |