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authorTony Lindgren <tony@atomide.com>2009-05-26 14:41:35 -0700
committerTony Lindgren <tony@atomide.com>2009-05-26 14:41:35 -0700
commit88b6f7eb9b4a06fbfe27f2d98e249577f4cfdaef (patch)
tree9ef0d7ecd3e0551ca4d13ac0134aeb3ecd8558c7 /arch/arm/plat-omap/sram.c
parent8f9ccfeeb2cecb54dd093119291ab271ab0fd94a (diff)
parent7971687094ef48695aa56a0c03416b609bd4d1fd (diff)
Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into for-next
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
-rw-r--r--arch/arm/plat-omap/sram.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e1493d83a7c..4f0145d2624 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -201,6 +201,15 @@ void __init omap_map_sram(void)
base = OMAP3_SRAM_PA;
base = ROUND_DOWN(base, PAGE_SIZE);
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+
+ /*
+ * SRAM must be marked as non-cached on OMAP3 since the
+ * CORE DPLL M2 divider change code (in SRAM) runs with the
+ * SDRAM controller disabled, and if it is marked cached,
+ * the ARM may attempt to write cache lines back to SDRAM
+ * which will cause the system to hang.
+ */
+ omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
}
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
@@ -343,14 +352,15 @@ static inline int omap243x_sram_init(void)
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
- u32 m2);
+ u32 m2, u32 unlock_dll);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
- u32 sdrc_actim_ctrlb, u32 m2)
+ u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
{
BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
- sdrc_actim_ctrlb, m2);
+ sdrc_actim_ctrlb, m2,
+ unlock_dll);
}
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */