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authorAnand Gadiyar <gadiyar@ti.com>2009-01-15 13:09:53 +0200
committerTony Lindgren <tony@atomide.com>2009-01-15 13:09:53 +0200
commit4b3cf44846b6424d4119676ad68d54a62b81e31c (patch)
treedcf09df49e55541bf115da40155add60b7ed0590 /arch/arm/plat-omap
parent3a26e3318bc2ceec340f242c6ee7074becdc7219 (diff)
ARM: OMAP: Fix DMA CCR programming for request line > 63, v3
Bug in existing code causes synchro control to be set +32 if request line greater than 63 is used. Also clean up the function a bit by removing extra parens and clearing the bits at before write. Reported by Wenbiao Wang. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/dma.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 692d2b495af..e77373c39f8 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -278,14 +278,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
u32 val;
val = dma_read(CCR(lch));
- val &= ~(3 << 19);
- if (dma_trigger > 63)
- val |= 1 << 20;
- if (dma_trigger > 31)
- val |= 1 << 19;
-
- val &= ~(0x1f);
- val |= (dma_trigger & 0x1f);
+
+ /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
+ val &= ~((3 << 19) | 0x1f);
+ val |= (dma_trigger & ~0x1f) << 14;
+ val |= dma_trigger & 0x1f;
if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5;