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authorSaeed Bishara <saeed@marvell.com>2008-11-27 06:21:03 -1100
committerNicolas Pitre <nico@cam.org>2008-12-02 16:53:26 -0500
commit82676d76252680fc035247fd4cfdb07ffce5db52 (patch)
tree6d6904370e364c279533a3db8c023fa1fe544bf8 /arch/arm/plat-orion
parent020f97063dd68a8e3b9aac928ac49a438b7416ce (diff)
[ARM] Orion: fix bug in pcie configuration cycle function field mask
The function field is 3 bits. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/plat-orion')
-rw-r--r--arch/arm/plat-orion/pcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 883902fead8..d41d41d78ad 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -35,7 +35,7 @@
#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
-#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
+#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
#define PCIE_CTRL_OFF 0x1a00