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authorTomi Valkeinen <tomi.valkeinen@nokia.com>2009-01-27 19:44:31 -0700
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 17:50:31 +0000
commit054ce503ae335dbc8610ef5aa0852c0c090023fe (patch)
tree31732b54d68aac75054b7a2affd0e1ccc369a43f /arch/arm
parentbe48ea74d49408c5c4f999c730d35eaf0034f273 (diff)
[ARM] OMAP: wait for pwrdm transition after clk_enable()
Enabling clock in a disabled power domain causes the power domain to be turned on. However, the power transition is not always finished when clk_enable() returns and this randomly crashes the kernel when an interrupt happens right after the clk_enable, and the kernel tries to read the irq status register for that domain. Why the irq status register is inaccessible, I don't know. Also it doesn't seem to be related to the module being not powered up, but to the transition itself. The same could perhaps happen after clk_disable also, but I have not witnessed that. The problem affects at least dss, cam and sgx clocks. This change waits for the transition to be finished before returning from omap2_clkdm_clk_enable(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/clockdomain.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index e9b4f6c564e..c9c367c3967 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -568,6 +568,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+
return 0;
}