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authorBen Dooks <ben-linux@fluff.org>2008-11-03 14:56:25 +0000
committerBen Dooks <ben-linux@fluff.org>2008-12-15 23:50:22 +0000
commit44539a711217898358ae456fc0f81f5f4652abd5 (patch)
treee8782de9f622f06c16a6d74599aeb6e3bc63e83d /arch/arm
parent6a5f4b8535868ada539ea2479d4f0a6c694b3908 (diff)
[ARM] S3C64XX: Fix MMC0 clock source register mask
Fix the definition of the MMC0 register shift and mask in the CLKSRC register. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-clock.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 78938a5e1d2..b1082c16324 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -205,8 +205,8 @@
#define S3C6400_CLKSRC_MMC2_SHIFT (22)
#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
#define S3C6400_CLKSRC_MMC1_SHIFT (20)
-#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1)
-#define S3C6400_CLKSRC_MMC0_SHIFT (1)
+#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
+#define S3C6400_CLKSRC_MMC0_SHIFT (18)
#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
#define S3C6400_CLKSRC_SPI1_SHIFT (16)
#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)