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| author | Paul Walmsley <paul@pwsan.com> | 2009-06-19 19:08:24 -0600 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-06-19 19:09:30 -0600 |
| commit | 6adb8f388ef2f23d4a81e1e42d15f22d62749a06 (patch) | |
| tree | 217206b7b4751b6644e3cbe91cfff8e4df861e48 /arch/arm | |
| parent | cd07ecc828486e5887113c7dc4d9f9022145811b (diff) | |
OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider. This does not appear
to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-omap2/sram34xx.S | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index c080c82521e..84781a6cd26 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -102,9 +102,6 @@ configure_core_dpll: orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val str r12, [r11] ldr r12, [r11] @ posted-write barrier for CM - mov r12, #0x800 @ wait for the clock to stabilise - cmp r3, #2 - bne wait_clk_stable bx lr wait_clk_stable: subs r12, r12, #1 |