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authorHans-Christian Egtvedt <hcegtvedt@atmel.com>2007-06-04 16:10:57 +0200
committerHaavard Skinnemoen <hskinnemoen@atmel.com>2007-07-18 20:45:51 +0200
commit9e58e1855c9815ad4944df90f695a7645c50f463 (patch)
tree22bf85cd9a42039726de7c5250f30207dad36b5f /arch/avr32/mach-at32ap/at32ap7000.c
parent7a5b80590772c29bba1d54d3685622177d6fe39f (diff)
[AVR32] CPU frequency scaling for AT32AP
This patch enables CPU frequency scaling for AT32AP devices. This will enable the CPU to scale between the speed of the high speed bus and the master clock and thus save some power. The patch also adds a parent to cpu_clk and a cpu_clk_set_rate to enable changing the CPU clock divider in a sane way. The driver does not check if the given rate is 0, thus resulting in a div by 0. I think this check should be go into the clk_set_rate framework, and not here. Tested on AT32AP7000/ATSTK1000. Hardware documentation can be found in the AT32AP7000 datasheet. Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/mach-at32ap/at32ap7000.c')
-rw-r--r--arch/avr32/mach-at32ap/at32ap7000.c43
1 files changed, 41 insertions, 2 deletions
diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
index 5faa97e5ab1..c74f3715f3f 100644
--- a/arch/avr32/mach-at32ap/at32ap7000.c
+++ b/arch/avr32/mach-at32ap/at32ap7000.c
@@ -219,6 +219,41 @@ static unsigned long cpu_clk_get_rate(struct clk *clk)
return bus_clk_get_rate(clk, shift);
}
+static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+ u32 control;
+ unsigned long parent_rate, child_div, actual_rate, div;
+
+ parent_rate = clk->parent->get_rate(clk->parent);
+ control = pm_readl(CKSEL);
+
+ if (control & PM_BIT(HSBDIV))
+ child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
+ else
+ child_div = 1;
+
+ if (rate > 3 * (parent_rate / 4) || child_div == 1) {
+ actual_rate = parent_rate;
+ control &= ~PM_BIT(CPUDIV);
+ } else {
+ unsigned int cpusel;
+ div = (parent_rate + rate / 2) / rate;
+ if (div > child_div)
+ div = child_div;
+ cpusel = (div > 1) ? (fls(div) - 2) : 0;
+ control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
+ actual_rate = parent_rate / (1 << (cpusel + 1));
+ }
+
+ pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
+ clk->name, rate, actual_rate);
+
+ if (apply)
+ pm_writel(CKSEL, control);
+
+ return actual_rate;
+}
+
static void hsb_clk_mode(struct clk *clk, int enabled)
{
unsigned long flags;
@@ -300,6 +335,7 @@ static unsigned long pbb_clk_get_rate(struct clk *clk)
static struct clk cpu_clk = {
.name = "cpu",
.get_rate = cpu_clk_get_rate,
+ .set_rate = cpu_clk_set_rate,
.users = 1,
};
static struct clk hsb_clk = {
@@ -1152,10 +1188,13 @@ void __init at32_clock_init(void)
u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
int i;
- if (pm_readl(MCCTRL) & PM_BIT(PLLSEL))
+ if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
main_clock = &pll0;
- else
+ cpu_clk.parent = &pll0;
+ } else {
main_clock = &osc0;
+ cpu_clk.parent = &osc0;
+ }
if (pm_readl(PLL0) & PM_BIT(PLLOSC))
pll0.parent = &osc1;