diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2008-11-18 17:48:22 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 17:48:22 +0800 |
| commit | dc26aec25d1a4e2690df166dbe843344728994ce (patch) | |
| tree | 36717399eff88602af964f9f80814f9210698d95 /arch/blackfin/mach-bf538/include/mach/dma.h | |
| parent | f940260a980a1ad7570dfd7a4b73c6ad2207f738 (diff) | |
Blackfin arch: BF538/9 Linux kernel Support
Add supporing for Blackfin BF538 and BF539 processors.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf538/include/mach/dma.h')
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/dma.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h new file mode 100644 index 00000000000..c2210a996e6 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/dma.h @@ -0,0 +1,65 @@ +/* + * file: include/asm-blackfin/mach-bf538/dma.h + * based on: + * author: + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MACH_DMA_H_ +#define _MACH_DMA_H_ + +#define CH_PPI 0 +#define CH_SPORT0_RX 1 +#define CH_SPORT0_TX 2 +#define CH_SPORT1_RX 3 +#define CH_SPORT1_TX 4 +#define CH_SPI0 5 +#define CH_UART0_RX 6 +#define CH_UART0_TX 7 +#define CH_SPORT2_RX 8 +#define CH_SPORT2_TX 9 +#define CH_SPORT3_RX 10 +#define CH_SPORT3_TX 11 +#define CH_SPI1 14 +#define CH_SPI2 15 +#define CH_UART1_RX 16 +#define CH_UART1_TX 17 +#define CH_UART2_RX 18 +#define CH_UART2_TX 19 + +#define CH_MEM_STREAM0_DEST 20 +#define CH_MEM_STREAM0_SRC 21 +#define CH_MEM_STREAM1_DEST 22 +#define CH_MEM_STREAM1_SRC 23 +#define CH_MEM_STREAM2_DEST 24 +#define CH_MEM_STREAM2_SRC 25 +#define CH_MEM_STREAM3_DEST 26 +#define CH_MEM_STREAM3_SRC 27 + +#define MAX_BLACKFIN_DMA_CHANNEL 28 + +#endif |