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authorMike Frysinger <vapier@gentoo.org>2009-05-14 14:55:50 +0000
committerMike Frysinger <vapier@gentoo.org>2009-06-12 06:11:24 -0400
commitc8f36dc3c11c3e9e879ded82cdf5d748d4ab2fb2 (patch)
tree27ebc3fbb08a15f1561d20ed8f90c12c230db6a2 /arch/blackfin/mach-bf561/Kconfig
parentb9ccf14bc5352b86e7e254e6cf55d9b917b1b1cc (diff)
Blackfin: simplify BF561 coreb driver greatly
Since 90% of this driver can be handled in user space, move it to the corebld user space application. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/Kconfig')
-rw-r--r--arch/blackfin/mach-bf561/Kconfig15
1 files changed, 1 insertions, 14 deletions
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
index 638ec38ca47..6965dd59af4 100644
--- a/arch/blackfin/mach-bf561/Kconfig
+++ b/arch/blackfin/mach-bf561/Kconfig
@@ -9,22 +9,9 @@ if (!SMP)
comment "Core B Support"
config BF561_COREB
- bool "Enable Core B support"
+ bool "Enable Core B loader"
default y
-config BF561_COREB_RESET
- bool "Enable Core B reset support"
- default n
- help
- This requires code in the application that is loaded
- into Core B. In order to reset, the application needs
- to install an interrupt handler for Supplemental
- Interrupt 0, that sets RETI to 0xff600000 and writes
- bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
- This causes Core B to stall when Supplemental Interrupt
- 0 is set, and will reset PC to 0xff600000 when
- COREB_SRAM_INIT is cleared.
-
endif
comment "Interrupt Priority Assignment"