diff options
author | H. Peter Anvin <hpa@zytor.com> | 2009-08-26 17:17:51 -0700 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2009-08-26 17:24:28 -0700 |
commit | b855192c08fcb14adbc5d3a7cab182022d433cca (patch) | |
tree | 3a10cafbfbf98cafacf667eb218c71300b351bfa /arch/blackfin/mach-bf561/include/mach/mem_map.h | |
parent | d886c73cd4cf02a71e1650cbcb6176799d78aac1 (diff) | |
parent | 3e0e1e9c5a327d4dba8490d83ef55c0564e6e8a7 (diff) |
Merge branch 'x86/urgent' into x86/pat
Reason: Change to is_new_memtype_allowed() in x86/urgent
Resolved semantic conflicts in:
arch/x86/mm/pat.c
arch/x86/mm/ioremap.c
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/mem_map.h')
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/mem_map.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index a63e15c86d9..5b96ea549a0 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -37,7 +37,6 @@ /* Memory Map for ADSP-BF561 processors */ -#ifdef CONFIG_BF561 #define COREA_L1_CODE_START 0xFFA00000 #define COREA_L1_DATA_A_START 0xFF800000 #define COREA_L1_DATA_B_START 0xFF900000 @@ -74,6 +73,28 @@ #define BFIN_DCACHESIZE (0*1024) #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ + +/* + * If we are in SMP mode, then the cache settings of Core B will match + * the settings of Core A. If we aren't, then we assume Core B is not + * using any cache. This allows the rest of the kernel to work with + * the core in either mode as we are only loading user code into it and + * it is the user's problem to make sure they aren't doing something + * stupid there. + * + * Note that we treat the L1 code region as a contiguous blob to make + * the rest of the kernel simpler. Easier to check one region than a + * bunch of small ones. Again, possible misbehavior here is the fault + * of the user -- don't try to use memory that doesn't exist. + */ +#ifdef CONFIG_SMP +# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH +# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH +# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH +#else +# define COREB_L1_CODE_LENGTH 0x14000 +# define COREB_L1_DATA_A_LENGTH 0x8000 +# define COREB_L1_DATA_B_LENGTH 0x8000 #endif /* Level 2 Memory */ |