aboutsummaryrefslogtreecommitdiff
path: root/arch/blackfin/mach-common/cache.S
diff options
context:
space:
mode:
authorIngo Molnar <mingo@elte.hu>2009-03-12 13:16:18 +0100
committerIngo Molnar <mingo@elte.hu>2009-03-12 13:16:18 +0100
commitf8cb22cbb8383c9f41e6ccbcd4fb94edb1048bda (patch)
tree9b3a333224ec895c053a694dcaff526502b84e6c /arch/blackfin/mach-common/cache.S
parent044d408409cc4e1bc75c886e27ca85c270db104c (diff)
parentebdcc81c71937b30e09110c02a1e8a21fa770b6f (diff)
Merge branch 'linus' into irq/genirq
Diffstat (limited to 'arch/blackfin/mach-common/cache.S')
-rw-r--r--arch/blackfin/mach-common/cache.S22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf28..aa0648c6a9f 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -66,11 +66,33 @@
/* Invalidate all instruction cache lines assocoiated with this memory area */
ENTRY(_blackfin_icache_flush_range)
+/*
+ * Walkaround to avoid loading wrong instruction after invalidating icache
+ * and following sequence is met.
+ *
+ * 1) One instruction address is cached in the instruction cache.
+ * 2) This instruction in SDRAM is changed.
+ * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
+ * 4) This instruction is executed again, but the old one is loaded.
+ */
+ P0 = R0;
+ IFLUSH[P0];
do_flush IFLUSH, , nop
ENDPROC(_blackfin_icache_flush_range)
/* Flush all cache lines assocoiated with this area of memory. */
ENTRY(_blackfin_icache_dcache_flush_range)
+/*
+ * Walkaround to avoid loading wrong instruction after invalidating icache
+ * and following sequence is met.
+ *
+ * 1) One instruction address is cached in the instruction cache.
+ * 2) This instruction in SDRAM is changed.
+ * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
+ * 4) This instruction is executed again, but the old one is loaded.
+ */
+ P0 = R0;
+ IFLUSH[P0];
do_flush FLUSH, IFLUSH
ENDPROC(_blackfin_icache_dcache_flush_range)