Blackfin arch: Start untangling the CPLB handling code.

 - Move cache initialization to C from assembly.
 - Move anomaly workaround for writing [ID]MEM_CONTROL to assembly, so
   that we don't have to mess around with .align directives in C source.
 - Fix a bug where bfin_write_DMEM_CONTROL would write to IMEM_CONTROL
 - Break out CPLB related code from kernel/setup.c into their own file.
 - Don't define variables in header files, only declare them.

Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

1 files changed, 11 insertions, 78 deletions

diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 7924a90d965..9d475623b72 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,104 +38,37 @@
 
 .text
 
+#ifdef ANOMALY_05000125
 #if defined(CONFIG_BLKFIN_CACHE)
-ENTRY(_bfin_icache_init)
+ENTRY(_bfin_write_IMEM_CONTROL)
 
-	/* Initialize Instruction CPLBS */
-
-	I0.L = (ICPLB_ADDR0 & 0xFFFF);
-	I0.H = (ICPLB_ADDR0 >> 16);
-
-	I1.L = (ICPLB_DATA0 & 0xFFFF);
-	I1.H = (ICPLB_DATA0 >> 16);
-
-	I2.L = _icplb_table;
-	I2.H = _icplb_table;
-
-	r1 = -1;	/* end point comparison */
-	r3 = 15;	/* max counter */
-
-/* read entries from table */
-
-.Lread_iaddr:
-	R0 = [I2++];
-	CC = R0 == R1;
-	IF CC JUMP .Lidone;
-	[I0++] = R0;
-
-.Lread_idata:
-	R2 = [I2++];
-	[I1++] = R2;
-	R3 = R3 + R1;
-	CC = R3 == R1;
-	IF !CC JUMP .Lread_iaddr;
-
-.Lidone:
 	/* Enable Instruction Cache */
 	P0.l = (IMEM_CONTROL & 0xFFFF);
 	P0.h = (IMEM_CONTROL >> 16);
-	R1 = [P0];
-	R0 = (IMC | ENICPLB);
-	R0 = R0 | R1;
 
 	/* Anomaly 05000125 */
-	CLI R2;
+	CLI R1;
 	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
 	.align 8;
 	[P0] = R0;
 	SSYNC;
-	STI R2;
+	STI R1;
 	RTS;
 
-ENDPROC(_bfin_icache_init)
+ENDPROC(_bfin_write_IMEM_CONTROL)
 #endif
 
 #if defined(CONFIG_BLKFIN_DCACHE)
-ENTRY(_bfin_dcache_init)
-
-	/* Initialize Data CPLBS */
-
-	I0.L = (DCPLB_ADDR0 & 0xFFFF);
-	I0.H = (DCPLB_ADDR0 >> 16);
-
-	I1.L = (DCPLB_DATA0 & 0xFFFF);
-	I1.H = (DCPLB_DATA0 >> 16);
-
-	I2.L = _dcplb_table;
-	I2.H = _dcplb_table;
-
-	R1 = -1;	/* end point comparison */
-	R3 = 15;	/* max counter */
-
-	/* read entries from table */
-.Lread_daddr:
-	R0 = [I2++];
-	cc = R0 == R1;
-	IF CC JUMP .Lddone;
-	[I0++] = R0;
-
-.Lread_ddata:
-	R2 = [I2++];
-	[I1++] = R2;
-	R3 = R3 + R1;
-	CC = R3 == R1;
-	IF !CC JUMP .Lread_daddr;
-.Lddone:
-	P0.L = (DMEM_CONTROL & 0xFFFF);
-	P0.H = (DMEM_CONTROL >> 16);
-	R1 = [P0];
-
-	R0 = DMEM_CNTR;
-
-	R0 = R0 | R1;
-	/* Anomaly 05000125 */
-	CLI R2;
+ENTRY(_bfin_write_DMEM_CONTROL)
+	CLI R1;
 	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
 	.align 8;
 	[P0] = R0;
 	SSYNC;
-	STI R2;
+	STI R1;
 	RTS;
 
-ENDPROC(_bfin_dcache_init)
+ENDPROC(_bfin_write_DMEM_CONTROL)
+#endif
+
 #endif