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| author | Jeff Garzik <jgarzik@pobox.com> | 2005-10-06 05:51:07 -0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-10-06 05:51:07 -0400 |
| commit | 012e060c95e547eceea4a12c6f58592473bf4011 (patch) | |
| tree | b57d3eafb50ce517577d2cf366c9ef0b4b286589 /arch/i386/kernel/cpu/amd.c | |
| parent | 923f122573851d18a3832ca808269fa2d5046fb1 (diff) | |
| parent | ed39f731ab2e77e58122232f6e27333331d7793d (diff) | |
Merge branch 'master'
Diffstat (limited to 'arch/i386/kernel/cpu/amd.c')
| -rw-r--r-- | arch/i386/kernel/cpu/amd.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index 73aeaf5a9d4..4c1ddf2b57c 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -28,6 +28,22 @@ static void __init init_amd(struct cpuinfo_x86 *c) int mbytes = num_physpages >> (20-PAGE_SHIFT); int r; +#ifdef CONFIG_SMP + unsigned long value; + + /* Disable TLB flush filter by setting HWCR.FFDIS on K8 + * bit 6 of msr C001_0015 + * + * Errata 63 for SH-B3 steppings + * Errata 122 for all steppings (F+ have it disabled by default) + */ + if (c->x86 == 15) { + rdmsrl(MSR_K7_HWCR, value); + value |= 1 << 6; + wrmsrl(MSR_K7_HWCR, value); + } +#endif + /* * FIXME: We should handle the K5 here. Set up the write * range and also turn on MSR 83 bits 4 and 31 (write alloc, |