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authorShaohua Li <shaohua.li@intel.com>2006-03-23 02:59:52 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-23 07:38:06 -0800
commitf2d0d263b51d13efe55f0aae9254b69ba2855f1c (patch)
treea392ca227a460b22fe90cc5bca73e18e0b70cbdb /arch/i386/kernel/cpu
parent75874d5cc8efef22457072e14103dc55f164e64e (diff)
[PATCH] x86: cpuid.4 doesn't need cpu level 5
Detecting cache line using cpuid.4, cpuid level 4 is enough. Signed-off-by: Shaohua Li<shaohua.li@intel.com> Cc: Dave Jones <davej@codemonkey.org.uk> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/i386/kernel/cpu')
-rw-r--r--arch/i386/kernel/cpu/intel_cacheinfo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index 36c9b370663..ce61921369e 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -174,7 +174,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
- if (c->cpuid_level > 4) {
+ if (c->cpuid_level > 3) {
static int is_initialized;
if (is_initialized == 0) {