diff options
| author | Xu, Anthony <anthony.xu@intel.com> | 2006-01-09 10:36:35 +0800 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2006-01-16 15:44:53 -0800 |
| commit | f15ac5801fdc1b217c3b8b5dbc63a09371d2ee4d (patch) | |
| tree | b9d4eeb9b5a6ab36fdaebf24263aa4ba5543aec7 /arch/ia64/sn/pci/pcibr | |
| parent | 7b9c8ba2d634a0467a8a36018a28624563f34f47 (diff) | |
[IA64] pal cache flush patch
Because PAL spec has changed since 2002, you can goto
http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm to
download new SDM, all PAL calls should be invoked with psr.ic=1, and
it's caller's responsibility to handle possible tlb miss.
Ia64_pal_cache_flush was written according to old spec, it is obsolete,
and this patch has ia64_pal_cache_flush conform to new spec.
Signed-off-by Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/sn/pci/pcibr')
0 files changed, 0 insertions, 0 deletions