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authorMark Maule <maule@sgi.com>2005-04-25 13:18:02 -0700
committerTony Luck <tony.luck@intel.com>2005-04-25 13:18:02 -0700
commit4628d7cada7a19166ba8fe57f5ef0f0009694e1e (patch)
tree86fa31598303768755a4caeee662b4c999c3a929 /arch/ia64
parente96c9b4779e651a7469bea677be3a08f70be399e (diff)
[IA64-SGI] disable TIOCA GART TLB prefetching
Patch to disable SGI TIOCA GART TLB prefetching due to hw bug. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/sn/pci/tioca_provider.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 2234d61cdd4..54a0dd447e7 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -171,15 +171,15 @@ tioca_gart_init(struct tioca_kernel *tioca_kern)
* use agp op-combining
* use GET semantics to fetch memory
* participate in coherency domain
- * prefetch TLB entries
+ * DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
*/
ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY; /* PV895469 ? */
ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
tioca_kern->ca_gart_iscoherent = 1;
- ca_base->ca_control2 |=
- (CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
+ ca_base->ca_control2 &=
+ ~(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
/*
* Unmask GART fetch error interrupts. Clear residual errors first.