diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-17 09:52:43 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-17 09:52:43 -0700 |
commit | 66bc4a6f34a950c7aede597c578352c3eba82017 (patch) | |
tree | d8005bd9abc0209cff47072d7e48cf19fddc52f5 /arch/m68k/include/asm/m5249sim.h | |
parent | 96c015b75feaaa67c8744229937bd9c35919d16b (diff) | |
parent | 2985709d7f3078c7609ae7f16affc0fb478d7d7a (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (53 commits)
m68knommu: Make PAGE_SIZE available to assembly files.
m68knommu: fix ColdFire definition of CLOCK_TICK_RATE
m68knommu: set multi-function pins for ethernet when enabled
m68knommu: remove special interrupt handling code for ne2k support
m68knommu: relax IO_SPACE_LIMIT setting
m68knommu: remove ColdFire direct interrupt register access
m68knommu: create a speciailized ColdFire 5272 interrupt controller
m68knommu: add support for second interrupt controller of ColdFire 5249
m68knommu: clean up old ColdFire timer irq setup
m68knommu: map ColdFire interrupts to correct masking bits
m68knommu: clean up ColdFire 532x CPU timer setup
m68knommu: simplify ColdFire "timers" clock initialization
m68knommu: support code to mask external interrupts on old ColdFire CPU's
m68knommu: merge old ColdFire interrupt controller masking macros
m68knommu: remove duplicate ColdFire mcf_autovector() code
m68knommu: move ColdFire INTC definitions to new include file
m68knommu: mask off all interrupts in ColdFire intc-simr controller
m68knommu: remove timer device interrupt setup for ColdFire 532x
m68knommu: remove interrupt masking from ColdFire pit timer
m68knommu: remove unecessary interrupt level setting in ColdFire 520x setup
...
Diffstat (limited to 'arch/m68k/include/asm/m5249sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 54 |
1 files changed, 34 insertions, 20 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 366eb8602d2..14bce877ed8 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -71,16 +71,22 @@ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ /* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ + +/* * General purpose IO registers (in MBAR2). */ -#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */ -#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */ -#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */ -#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */ -#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */ -#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */ -#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */ -#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */ +#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ +#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ +#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ +#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ +#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ +#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ +#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ +#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ #define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ #define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ @@ -100,20 +106,28 @@ #define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ #define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ - /* - * Macro to set IMR register. It is 32 bits on the 5249. + * Define the base interrupt for the second interrupt controller. + * We set it to 128, out of the way of the base interrupts, and plenty + * of room for its 64 interrupts. */ -#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */ +#define MCFINTC2_VECBASE 128 -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) +#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32) +#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33) +#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34) +#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35) +#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36) +#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37) +#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38) +#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39) -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) +/* + * Generic GPIO support + */ +#define MCFGPIO_PIN_MAX 64 +#define MCFGPIO_IRQ_MAX -1 +#define MCFGPIO_IRQ_VECBASE -1 /****************************************************************************/ @@ -137,9 +151,9 @@ subql #1,%a1 /* get MBAR2 address in a1 */ /* - * Move secondary interrupts to base at 128. + * Move secondary interrupts to their base (128). */ - moveb #0x80,%d0 + moveb #MCFINTC2_VECBASE,%d0 moveb %d0,0x16b(%a1) /* interrupt base register */ /* |